(1) Field of the Invention
The present invention relates to MOS solid-state imaging devices, and more particularly to a MOS solid-state imaging device having column amplifier circuits and a driving method of the solid-state imaging device.
(2) Description of the Related Art
In recent years, Metal Oxide Semiconductor (MOS) solid-state imaging devices, also known as amplifier-type solid-state imaging devices have been replacing Charge Coupled Device (CCD) solid-state imaging devices. While a CCD solid-state imaging device transfers signal charge Q generated and accumulated in photodiodes (PDs) to vertical and horizontal direction by a transfer pulse made up of multiple voltages, converts the charge into voltage (Q-V), and outputs by a floating diffusion amplifier (FDA) provided at an output terminal of the device, a general MOS solid-state imaging device performs Q-V conversion per pixel by providing the FDA for pixels, and performs column parallel reading out by a single power supply (read out pixel signals in each column in parallel).
Recently the MOS solid-state imaging device has become the mainstream since the MOS solid-state imaging device can be driven by a single power supply by providing an FDA for the pixels, does not require special manufacturing process as for CCD, an analog circuit and a digital circuit can be provided in the same chip, and thus image signal can be easily processed.
In addition, some of recent MOS solid-state imaging devices include column amplifier circuits for each column for amplifying pixel signals. A general MOS solid-state imaging device is provided with a coupled double sampling (CDS) circuit to remove fixed pattern noise (FPN) which is generated in the pixels per column, and an output amplifier circuit for amplifying and outputting the signals. Here, providing the column amplifier circuits enables signals to be amplified with respect to the FPN and random noise generated in these circuits, and a bandwidth can be restricted by column parallel process, high signal/noise ratio (S/N) can be realized.
FIG. 1 shows a block diagram of a general MOS solid-state imaging device including column amplifier circuits.
FIG. 1 shows that the MOS solid-state imaging device having column amplifier circuits includes: a pixel circuit (pixel array) 101 including plural pixels 101a arranged in a matrix; a vertical scanning circuit 102 which selects the pixels 101a per row; vertical signal lines 103 commonly connected to the pixels 101a in each column; and column amplifier circuits 104 each of which is connected to each of the vertical signal lines 103. The output of each of the column amplifier circuits 104 is connected to column CDS circuits 105, and output signals are sequentially read out to a horizontal common signal line 107 using selection signals from a horizontal scanning circuit 106. An output amplifier circuit 108 is connected to the horizontal common signal line 107, and the amplified output signals are outputted from the solid-state imaging device via the output amplifier circuit 108.
Next, FIG. 2 shows a circuit diagram of the pixel circuit 101 and the row amplifier circuit 104 of the general MOS solid-state imaging device including column amplifier circuits.
FIG. 2 shows that the pixel circuit 101 includes the pixel 101a, the vertical signal line 103 and a current source load transistor NM 104. The pixel 101a includes a photodiode (PD) 201 which generates signal charges according to incident light and accumulate the signal charges, and a floating diffusion (FD) 202 which accumulates the signal charges transferred from the PD 201. A charge transfer transistor NM102 is provided between the PD 201 and the FD 202, and a reset transistor NM101 is provided between the FD202 and the power supply signal line PIXPOW101. In addition, the gate of the charge transfer transistor NM102 is connected to a transfer signal line TR, and the gate of the reset transistor NM101 is connected to a reset signal line RS. The FD 202 is connected to the gate of the amplifier transistor NM103 connected between the vertical signal line 103 and the power supply signal line PIXPOW101. In addition, the amplifier transistor NM103 forms a source follower circuit along with the current supply load transistor NM104 connected to the vertical signal line 103, and outputs signal voltage corresponding to the signal voltage transferred from the PD 201 to the FD 202 to the vertical signal line 103. The column amplifier circuit 104 including a capacitance Cin 101, a common-source amplifier transistor NM 105, a resistance load transistor NM 107, and a clamp transistor NM 106 is connected to the vertical signal line 103.
Next, operations of the pixel circuit 101 and the column amplifier circuit 104 are explained with reference to the timing chart shown in FIG. 3.
First, at the timing between t1 and t2, the FD 202 in the pixel 101a is reset to the voltage of the power source signal line PIXPOW 101 via the reset transistor MN 101. At the same time, the column amplifier circuit 104 is reset by switching ON the clamp transistor NM 106 in the column amplifier circuit 104, and the clamp transistor NM 106 is switched OFF at timing t3. Subsequently, at the timing between t4 and t5, the signal charge Q accumulated in the PD 201 is transferred to the FD 202 by switching ON the charge transfer transistor NM 102 in the pixel circuit 101. With this, Q-V conversion is performed by the capacitance Cfd of the FD 202, and signal amplitude shown in the following formula is outputted to the vertical signal line 103 from the FD 202.
                    Q        Cfd                            [                  Formula          ⁢                                          ⁢          1                ]            
Here, a signal which is amplified by “A” times with respect to the output signal from the vertical signal line 103 as shown below is outputted as Vout from the column amplifier circuit 104.
                    A        ×                  Q          Cfd                                    [                  Formula          ⁢                                          ⁢          2                ]            
However, note that the gain of the source follower circuit is assumed to be 1.
Here, in a general solid-state imaging device including column amplifier circuits, since the power supply and the ground are supplied from a bonding pad provided at an end of a chip, each supply path more or less includes parasitic resistance Rvdd and Rgnd. Thus, when a single ended column amplifier as shown in FIG. 2 is provided, consumption current Iamp in the column amplifier circuit varies depending on the amplitude of the input signal to the column amplifier circuit as shown in FIG. 4. With this, the power source and ground voltage vary due to the parasitic resistance. There is a problem that, the variation in power supply voltage and the ground voltage in the column amplifier circuit appears as an output offset, an output offset is generated according to whether or not the signal of the high brightness object exists for the signals in other columns which has been read out simultaneously in parallel processing, and as shown in FIG. 5, the output offset appears in an output image as image defect such as a horizontal belt-like noise. In order to solve the problem, in Japanese Unexamined Patent Application Publication No. 2005-252529, a limiter transistor whose gate is connected to a limiter judging potential which judges output voltage of the amplifier, whose source is connected to the output of the amplifier, and whose drain is grounded is provided separately to a single ended switched capacitor amplifier (column amplifier circuit) in a column amplifier circuit in order to keep the consumption current of the column amplifier circuit at a constant value.